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Error: Iteration limit reached
Title
Question
What does the following error exactly describes ?

Error:
doAnalyses: iteration limit reached
run simulation(s) aborted
Error: no such vector v(11)


Oscad Schematic-Creation-and-Simulation 00-01 min 0-10 sec 01-05-14, 8:28 p.m. 7skysurfers

Answers:

There is something wrong with the circuit and hence the netlist. The simulator has tried to simulate but failed. Can you please copy - paste the netlist (file with the extension .cir.out) here?
01-05-14, 8:37 p.m. rakhiwarriar


* eeschema netlist version 1.1 (spice format) creation date: thu 01 may 2014 12:17:49 pm pdt

* 74ls32
* 74ls04
v5 2 0 dc 5
* Printing option vprint8_1
v4 15 0 dc 5
v3 6 0 dc 5
v2 9 0 dc 5
v1 10 0 dc 5
* 74ls32
* 74ls08
a1 [10] [10_in] u5adc
a2 [9] [9_in] u5adc
a3 [10_in 9_in] 3_out u5
a4 [3_out] [3] u5dac
a5 [3] [3_in] u5adc
a6 [2] [2_in] u5adc
a7 [3_in 2_in] 19_out u5
a8 [19_out] [19] u5dac
a9 [17] [17_in] u5adc
a10 [16] [16_in] u5adc
a11 [17_in 16_in] 18_out u5
a12 [18_out] [18] u5dac
.model u5 d_or
.model u5adc adc_bridge(in_low=0.8 in_high=2.0)
.model u5dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
a13 [15] [15_in] u1adc
a14 15_in 4_out u1
a15 [4_out] [4] u1dac
a16 [6] [6_in] u1adc
a17 6_in 8_out u1
a18 [8_out] [8] u1dac
a19 [19] [19_in] u1adc
a20 19_in 13_out u1
a21 [13_out] [13] u1dac
a22 [14] [14_in] u1adc
a23 14_in 18_out u1
a24 [18_out] [18] u1dac
.model u1 d_inverter
.model u1adc adc_bridge(in_low=0.8 in_high=2.0)
.model u1dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
a25 [5] [5_in] u3adc
a26 [12] [12_in] u3adc
a27 [5_in 12_in] 11_out u3
a28 [11_out] [11] u3dac
.model u3 d_or
.model u3adc adc_bridge(in_low=0.8 in_high=2.0)
.model u3dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)
a29 [6] [6_in] u2adc
a30 [4] [4_in] u2adc
a31 [6_in 4_in] 17_out u2
a32 [17_out] [17] u2dac
a33 [8] [8_in] u2adc
a34 [15] [15_in] u2adc
a35 [8_in 15_in] 16_out u2
a36 [16_out] [16] u2dac
a37 [19] [19_in] u2adc
a38 [18] [18_in] u2adc
a39 [19_in 18_in] 5_out u2
a40 [5_out] [5] u2dac
a41 [13] [13_in] u2adc
a42 [14] [14_in] u2adc
a43 [13_in 14_in] 12_out u2
a44 [12_out] [12] u2dac
.model u2 d_and
.model u2adc adc_bridge(in_low=0.8 in_high=2.0)
.model u2dac dac_bridge(out_low=0.25 out_high=5.0 out_undef=1.8 t_rise=0.5e-9 t_fall=0.5e-9)

.op

* Control Statements
.control
run
print v(11)
.endc
.end
01-05-14, 9:13 p.m. 7skysurfers
I will look into this. Can you also copy-paste the .cir file?
01-05-14, 9:58 p.m. rakhiwarriar
* EESchema Netlist Version 1.1 (Spice format) creation date: Thu 01 May 2014 12:17:49 PM PDT

* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0

*Sheet Name:/
U5 10 9 3 3 2 19 0 18 17 16 7 74LS32<span class="Apple-tab-span" style="white-space:pre"> </span>
U1 15 4 6 8 19 13 0 14 18 7 74LS04<span class="Apple-tab-span" style="white-space:pre"> </span>
v5 2 0 DC<span class="Apple-tab-span" style="white-space:pre"> </span>
U4 11 VPRINT8_1<span class="Apple-tab-span" style="white-space:pre"> </span>
v4 15 0 DC<span class="Apple-tab-span" style="white-space:pre"> </span>
v3 6 0 DC<span class="Apple-tab-span" style="white-space:pre"> </span>
v2 9 0 DC<span class="Apple-tab-span" style="white-space:pre"> </span>
v1 10 0 DC<span class="Apple-tab-span" style="white-space:pre"> </span>
U3 5 12 11 0 7 74LS32<span class="Apple-tab-span" style="white-space:pre"> </span>
U2 6 4 17 8 15 16 0 5 19 18 12 13 14 7 74LS08<span class="Apple-tab-span" style="white-space:pre"> </span>

.end
02-05-14, 10:46 a.m. Huzefa
What kind of analysis are you doing? Are you trying to do a tran analysis? tran analysis does not make any sense as there is no time dependent source in your circuit. Or you can give a pulse input and do a tran analysis.
By the way, you need not give separate DC power supply to each and every gate in your circuit. The netlist converter takes care of it. You need to give only a power flag (PWR_FLAG) at the Vcc terminal to indicate that there is a power source.You may want to check out the example on BasicGates in the Examples folder to get a better idea.
02-05-14, 4:11 p.m. rakhiwarriar
But what about the above question which i asked ?
I have tried that thing but it doesn't works everytime. So i m giving Vcc in every gate.
02-05-14, 4:41 p.m. Huzefa
See the above error "<span style="background-color: rgb(250, 250, 250);">doAnalyses: iteration limit reached</span>
<span style="background-color: rgb(250, 250, 250);">run simulation(s) aborted " - </span>just means your netlist has errors and simulation did not run successfully. So the next step is to figure out what the error in the circuit is. You did not answer my question above.
02-05-14, 4:45 p.m. rakhiwarriar
i m doing DC analysis for this circuit. but for pulse signal i mdoing trans. analysis

02-05-14, 5:15 p.m. Huzefa
I just did a KicadtoNgspice conversion for the .cir file above and gave a DC analysis for V1. I did not get any error. I did not see a PULSE signal in your circuit above.
You can remove all the DC sources that you have tied to the Vcc pins and give a PWR_FLAG there. Then do a DC analysis and let me know what you get.
02-05-14, 5:22 p.m. rakhiwarriar
Same error though i have removed all the source at vcc and gnd, by replacing just 1 pwr_flag
02-05-14, 5:38 p.m. Huzefa
Share the project zip folder here. You can use any free file uploading site to upload your file.
02-05-14, 5:41 p.m. rakhiwarriar
<a href="about:blank">EXAMPLE-4.7.zip</a> ....

02-05-14, 5:54 p.m. Huzefa
https://www.dropbox.com/s/dngg42caanusv5c/EXAMPLE-4.7.zip
02-05-14, 6:04 p.m. Huzefa
I am getting error iteration limit reached in simple digital circuit.I have drawn the circuit twice taken all the care about netlist generation also.. please suggest me a proper solution.
Thanks
03-05-14, 6:26 p.m. 7skysurfers
I have designed a circuit having 6 simple gates in digital electronics, the output is all ok. But I just added four NOT gates and it resulted in
"Error:
doAnalyses: iteration limit reached
run simulation(s) aborted"

So I concluded that increased no of gates created problem there. Which does not seem quite logical.
Please state the reason for the error and guide me.
Thanks..
03-05-14, 9:41 p.m. Ashoka_L
Sure, we will look into this.
03-05-14, 10:24 p.m. rakhiwarriar
When I replaced U1C-U1D-U2D combination with a NAND gate, it gets simulated correctly.
03-05-14, 11:24 p.m. rakhiwarriar
Thank you for your suggestion... it gets simulated correctly.
But can u tell me the reason for using of this alternative way?
Why the correct ans is not coming before replacing NAND gate?
04-05-14, 5:32 p.m. Huzefa
Well, if I understand correctly, it is because of the way we have modelled a digital IC in the backend. When an output drives multiple gates, particularly quad NOT gates, it creates a bug. (To be precise, this creates multiple paths between two nodes). One workaround is to replace redundant combinations with a relevant gate as we did above. We shall try to resolve this issue, as soon as possible.
04-05-14, 6:25 p.m. rakhiwarriar

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