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Unable to read analysis file
Title
Question
Circuit: * e:\gate\d_ff\d_ff.cir

Reducing trtol to 1 for xspice 'A' devices
Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

Warning: v1: no DC value, transient time 0 value used
Warning: v2: no DC value, transient time 0 value used
Warning: Too many iteration passes in event-driven circuits

Transient solution failed -

Last Node Voltages
------------------

Node                                   Last Voltage        Previous Iter
----                                   ------------        -------------
net-_u2-pad2_                                     0                    0
net-_u2-pad1_                                     0                    0
ff1                                               0                    0
ff2                                               0                    0
ff3                                               0                    0
ff4                                               0                    0
v1#branch                                         0                    0
v2#branch                                         0                    0
a7#branch_1_0                                     0                    0
a7#branch_1_1                                     0                    0
a7#branch_1_2                                     0                    0
a7#branch_1_3                                     0                    0


doAnalyses: iteration limit reached

run simulation(s) aborted
Error(parse.c--checkvalid): ff1: no such vector.
Error(parse.c--checkvalid): a7#branch_1_0: no such vector.
Error: no such vector ff4
Error: no such vector ff1
Error: no such vector ff3
Error: no such vector ff2
ngspice 1 -> 
Interrupted once . . .
Warning: clearing control structures
ngspice 1 -> 

eSim General None min None sec 25-04-23, 8:49 p.m. abhinav_trpth

Answers:

Dear Abhinav,

Please send the .cir.out file here.

Regards,
Sumanto Kar
eSim Team

25-04-23, 10:23 p.m. SumantoKar
<a href="https://drive.google.com/file/d/109nhvmp-gjd3sgqL2n4PrH4nB1g8k8TF/view?usp=sharing" target="" title="">https://drive.google.com/file/d/109nhvmp-gjd3sgqL2n4PrH4nB1g8k8TF/view?usp=sharing</a>
25-04-23, 11:21 p.m. abhinav_trpth

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<a href="https://drive.google.com/file/d/109nhvmp-gjd3sgqL2n4PrH4nB1g8k8TF/view?usp=sharing" target="" title="cir.out">cir.out</a>
Thank you sir for responding. I have pasted the link above
25-04-23, 11:19 p.m. abhinav_trpth


Dear Abhinav,

The netlist is erroneous there are a lot of question marks present in the netlist indicating wrong/no connection.  Also the units "ohms" need not be written after the Resistor values. Please recheck these things.

Please see the Spoken Tutorials videos to know how to create circuits in eSim:
https://spoken-tutorial.org/tutorial-search/?search_foss=eSim&search_language=English

Please feel free to ask if any queries.

Thanks & Regards,
Sumanto Kar

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Erroneous netlist:

* e:\gate\d_ff\d_ff.cir

* u6  net-_u3-pad2_ clk ? ? net-_u11-pad1_ ? d_dff
* u11  net-_u11-pad1_ clk ? ? net-_u11-pad5_ ? d_dff
* u12  net-_u11-pad5_ clk ? ? net-_u12-pad5_ net-_u12-pad6_ d_dff
* u4  net-_u3-pad3_ clk ? ? net-_u3-pad2_ ? d_dff
v1  net-_u2-pad1_ gnd pulse(0 5 5 0 0 5 10)
* u3  net-_u12-pad6_ net-_u3-pad2_ net-_u3-pad3_ d_nor
r1  gnd ff1 100ohm
r2  ff2 gnd 100ohm
r3  ff3 gnd 100ohm
r4  ff4 gnd 100ohm
* u10  ff4 plot_db
* u5  ff1 plot_db
* u1  clk plot_db
* u9  ff3 plot_db
* u8  ff2 plot_db
* u7  net-_u12-pad5_ net-_u11-pad5_ net-_u11-pad1_ net-_u3-pad2_ ff4 ff3 ff2 ff1 dac_bridge_4
* u2  net-_u2-pad1_ clk adc_bridge_1
a1 net-_u3-pad2_ clk ? ? net-_u11-pad1_ ? u6
a2 net-_u11-pad1_ clk ? ? net-_u11-pad5_ ? u11
a3 net-_u11-pad5_ clk ? ? net-_u12-pad5_ net-_u12-pad6_ u12
a4 net-_u3-pad3_ clk ? ? net-_u3-pad2_ ? u4
a5 [net-_u12-pad6_ net-_u3-pad2_ ] net-_u3-pad3_ u3
a6 [net-_u12-pad5_ net-_u11-pad5_ net-_u11-pad1_ net-_u3-pad2_ ] [ff4 ff3 ff2 ff1 ] u7
a7 [net-_u2-pad1_ ] [clk ] u2
* Schematic Name:                             d_dff, NgSpice Name: d_dff
.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             d_dff, NgSpice Name: d_dff
.model u11 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             d_dff, NgSpice Name: d_dff
.model u12 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             d_dff, NgSpice Name: d_dff
.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             d_nor, NgSpice Name: d_nor
.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name:                             dac_bridge_4, NgSpice Name: dac_bridge
.model u7 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
.tran 5e-03 100e-00 0e-00

* Control Statements 
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
plot db(ff4)
plot db(ff1)
plot db(clk)
plot db(ff3)
plot db(ff2)
.endc
.end



26-04-23, 12:17 a.m. SumantoKar


Okay Sir, I will be making a new circuit again from scratch.
Thank you sir
26-04-23, 12:20 a.m. abhinav_trpth


Sure, you are welcome. 
26-04-23, 1:13 a.m. SumantoKar


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